1. Field of the Invention
The present invention relates to a duty cycle correction circuit of a Delay Locked Loop (DLL) circuit and more particularly, to a duty cycle correction circuit of a DLL circuit in which the duty cycle of a DLL clock of a DLL circuit can be accurately set regardless of variation in an internal power supply voltage.
2. Discussion of Prior Art
In a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) device, data are input and output in synchronization with a rising edge and a falling edge of an external clock, respectively. Data that are output by the read operation of the DDR SDRAM must be accurately aligned with the edge of the external clock.
The DDR SDRAM delays a received external clock for a predetermined time and generates an internal clock. The input and output of data are synchronized with the internal clock. If the input and output of data are controlled in this manner, the data can be accurately aligned with the edge of the external clock.
At this time, a circuit that delays a received external clock for a predetermined time and generates an internal clock is referred to as a Delay Locked Loop (DLL) circuit.
To set the duty cycle of the DLL clock of the DLL circuit, a duty cycle correction circuit is used. The duty cycle correction circuit is not able to easily and accurately set the duty cycle of the DLL clock to 50% because of changes in PVT (Process, Voltage, Temperature). More particularly, if a DDR SDRAM device enters Active Power-Down Mode (APDM), a voltage comparator of the duty cycle correction circuit is reset and the operation of the duty cycle correction circuit is held, so that an analog output of a Digital/Analog (D/A) converter is not further updated.
FIG. 1 shows an operating timing diagram of a duty cycle correction circuit of a DLL circuit in the prior art.
As shown in FIG. 1, while in the APDM (from APDEN to APDEX), a voltage comparator (not shown) of the duty cycle correction circuit is reset according to a clock enable signal (CKE), so that the analog output signals (DCCFVREF, DCCRVREF) of a D/A converter (not shown) are not updated.
That is, if an internal power supply voltage is changed while in the APDM, the analog output signals (DCCFVREF, DCCRVREF) of the D/A converter are changed, as shown in FIG. 1. Therefore, the duty cycle of buffered clocks (FCKDCC, RCKDCC) output through a clock buffer/mux unit (not shown) does not become 50%. As a result, the duty cycle of the DLL clock does not become 50%.
If the APDM read operation is performed when the duty cycle of the DLL clock is deviated from 50%, tAC (DQ output access time from CK & /CK) or tCK (Clock cycle time) is changed due to the DLL clock whose duty cycle is deviated, resulting in a failed DRAM operation.